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ibm powerpc 750fx risc microprocessor datasheet (support for 750fx design revision level dd 2.x) version: 2.0 preliminary june 9, 2003
copyright and disclaimer ?copyright international business machines corporation 2003 all rights reserved printed in the united states of america june 2003 the following are trademarks of international business machines corporation in the united states, or other countries, or both. ibm ibm logo powerpc powerpc logo powerpc 750 powerpc architecture riscwatch other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in applications such as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this docu- ment was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is provided on an ?s is?basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www-3.ibm.com/chips/ title_750fx_ds_dd2.x.fm.2.0 june 9, 2003 preliminary note: this document contains information on products in the sampling and/or initial production phases of development. this information is subject to change without notice. verify with your ibm field applications engineer that you have the latest version of this document before finalizing a design.
datasheet dd 2.x preliminary powerpc 750fx risc microprocessor 750fx_ds_dd2.x_v2.02.fm.2.0 june 9, 2003 page 1 of 63 1. general information .................................................................................................... 3 1.1 features ................................................................................................................... ......................... 3 1.2 design level considerations and features ................................................................................... ... 5 1.3 processor version register ................................................................................................. ............. 5 1.4 part number information .................................................................................................... ............... 6 2. overview .................................................................................................................... .. 7 2.1 block diagram .............................................................................................................. ..................... 7 2.2 general parameters ......................................................................................................... ................. 8 3. electrical and thermal characteristics ..................................................................... 9 3.1 dc electrical characteristics .............................................................................................. ............... 9 3.2 clock ac specifications .................................................................................................... .............. 13 3.3 spread spectrum clock generator (sscg) ................................................................................... 1 4 3.5 60x bus output ac specifications ........................................................................................... ....... 17 3.6 alternate i/o timing for 3.3v bus .......................................................................................... ........ 19 3.6.1 ieee 1149.1 ac timing specifications ................................................................................. 20 4. dimensions and signal assignments ..................................................................... 22 4.1 module substrate decoupling voltage assignments ...................................................................... 22 4.2 package .................................................................................................................... ...................... 22 4.3 microprocessor ball placement .............................................................................................. ......... 24 5. system design information ..................................................................................... 31 5.1 pll considerations ......................................................................................................... ................ 31 5.1.1 restrictions and considerations for pll configuration ......................................................... 32 5.1.1.1 configuration restriction on frequency transitions ...................................................... 32 5.1.2 pll_rng[0:1] definitions for dual pll operation ................................................................ 32 5.1.3 pll configuration ........................................................................................................ .......... 33 5.2 pll power supply filtering ................................................................................................. ............ 35 5.3 decoupling recommendations ................................................................................................. ...... 39 5.4 output buffer dc impedance ................................................................................................. ......... 42 5.4.1 input-output usage ....................................................................................................... ........ 43 5.5 level protection ........................................................................................................... ................... 48 5.6 64 or 32-bit data bus mode ................................................................................................. ........... 49 5.7 iio voltage mode selection ................................................................................................. ........... 49 5.8 thermal management ......................................................................................................... ............ 49 5.8.1 heat sink selection example .............................................................................................. .. 49 5.8.2 internal package conduction .............................................................................................. .. 52 5.8.3 minimum heat sink requirements ........................................................................................ 53 5.8.4 heat sink mounting ....................................................................................................... ........ 54 5.8.5 thermal assist unit ...................................................................................................... ......... 54 5.8.6 adhesives and thermal interface materials .......................................................................... 55 5.8.7 thermal interface and adhesive vendors ............................................................................. 56 5.8.8 heat sink vendors ........................................................................................................ ......... 57 revision log ................................................................................................................ 5 9
datasheet dd 2.x powerpc 750fx risc microprocessor preliminary page 2 of 63 750fx_ds_dd2.x_v2.02.fm.2.0 june 9, 2003
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 1. general information page 3 of 63 1. general information the ibm powerpc 750fx risc microprocessor is a 32-bit implementation of the ibm powerpc family of reduced instruction set computer (risc) microprocessors. this document contains pertinent physical and electrical characteristics of the ibm powerpc 750fx risc microprocessor revision dd 2.x single chip modules (scm). the ibm powerpc 750fx risc microprocessor is also referred to as the 750fx throughout this document. 1.1 features this section summarizes the features of the 750fx implementation of the powerpc architecture. major features of the 750fx include the following: branch processing unit four instructions fetched per clock one branch processed per cycle (plus resolving two speculations) up to one speculative stream in execution, one additional speculative stream in fetch 512-entry branch history table (bht) for dynamic prediction 64-entry, 4-way set associative branch target instruction cache (btic) for eliminating branch delay slots decode register ?e access forwarding control partial instruction decode load/store unit one cycle load or store cache access (byte, half-word, word, double-word) effective address generation hits under miss (one outstanding miss) single-cycle misaligned access within double-word boundary alignment, zero padding, sign extend for integer register ?e floating-point internal format conversion (alignment, normalization) sequencing for load/store multiples and string operations store gathering cache and tlb instructions big and little-endian byte addressing supported misaligned little-endian support in hardware dispatch unit full hardware detection of dependencies (resolved in the execution units) dispatch two instructions to six independent units (system, branch, load/store, xed-point unit 1, ?ed-point unit 2, or ?ating-point) 4-stage pipeline: fetch, dispatch, execute, and complete serialization control (predispatch, postdispatch, execution, serialization) fixed-point units fixed-point unit 1 (fxu1): multiply, divide, shift, rotate, arithmetic, logical fixed-point unit 2 (fxu2): shift, rotate, arithmetic, logical single-cycle arithmetic, shift, rotate, logical multiply and divide support (multi-cycle) early out multiply thirty-two 32-bit general purpose registers floating-point unit support for ieee-754 standard single and double-precision ?ating-point arithmetic optimized for single-precision multiply/add thirty-two, 64-bit ?ating point registers enhanced reciprocal estimates 3-cycle latency, 1-cycle throughput, single-precision multiply-add 3-cycle latency, 1-cycle throughput, double-precision add 4-cycle latency, 2-cycle throughput, double-precision multiply-add hardware support for divide hardware support for denormalized numbers time deterministic non-ieee mode system unit executes cr logical instructions and mis- cellaneous system instructions special register transfer instructions .
body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 1. general information page 4 of 63 powerpc 750fx risc microprocessor preliminary l1 cache structure 32k, 32-byte line, 8-way set associative instruction cache 32k, 32-byte line, 8-way set associative data cache single-cycle cache access pseudo-lru replacement copy-back or write-through data cache (on a page per page basis) parity on l1 tags and arrays 3-state (mei) memory coherency hardware support for data coherency non-blocking instruction cache (one out- standing miss) non-blocking data cache (two outstanding misses) no snooping of instruction cache memory management unit 64 entry, 2-way set associative instruction tlb (total 128) 64 entry, 2-way set associative data tlb (total 128) hardware reload for tlbs 8 instruction bats and 8 data bats virtual memory support for up to 4 exabytes (2 52 ) virtual memory real memory support for up to 4 gigabytes (2 32 ) of physical memory support for big/little-endian addressing dual plls allows seamless frequency switching level 2 (l2) cache internal l2 cache controller and 4k-entry tags: 512kb data srams two-way set-associative, supports locking by way copy-back or write-through data cache on a page basis, or for all l2 64-byte sectored line size l2 frequency at core speed ecc protection on sram array parity on l2 tags supports up to 2 outstanding misses (1 data and 1 instruction or 2 data) ?ower low power consumption with low voltage application at lower frequency dynamic power management 3 static power save modes (doze, nap, and sleep) thermal assist unit (tau) bus interface 32-bit address bus 64-bit data bus (also supports 32-bit mode) enhanced 60x bus: pipelines consecutive reads to a depth of 2 core-to-bus frequency multipliers of 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 8.5x, 9x, 9.5x, 10x, 11x, 12x, 13x, 14x, 15x, 16x, 17x, 18x, 19x, and 20x supported supports 1.8v, 2.5v, or 3.3v i/o modes reliability and serviceability - parity checking on 60x interface - ecc checking on l2 cache - parity on the l1 arrays - parity on the l1 and l2 tags testability lssd scan design powerful diagnostic and test interface through common on-chip processor (cop) and ieee 1149.1 (jtag) interface
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 1. general information page 5 of 63 1.2 design level considerations and features the 750fx supports several unique features including those listed below. the ibm application note differ- ences between the powerpc 750fx, 750, 750cx, and 750cxe microprocessors provides a more detailed explanation of these features. incorporates an on-chip, 512k, two-way, set-associative l2 cache provides a 64 or 32-bit data bus mode (per setup of tlbisync pin) supports 1.8v, 2.5v, or 3.3v i/o modes implementation note: dd2.0 supports a limited use of the 3.3v i/o mode. for additional information, see the 750fx errata list of revision dd2.x . includes all 60x bus pins on earlier powerpc 750 designs and additional signals enhanced 60x bus ?for pipelined consecutive read transactions and higher frequency operation dual plls for additional power savings capabilities four additional ibat/dbat registers new cbga package with additional pins and depopulated footprint 1.3 processor version register the powerpc 750fx risc microprocessor has the following processor version register (pvr) values for the respective design revision levels. the 750fx pvr is 7000, which is not used in any previous powerpc processor design. table 1-1. 750fx processor version register (pvr) 750fx design revision level 750fx pvr dd2.0 0x700a02b0 dd2.1 0x700a02b1 dd2.2 0x700a02b2 dd2.3 0x700a02b3 note: 1. nibbles shown as ??are to be ignored, and are for factory use only. nibbles shown as ??may be 0 or 1 2. if l2_tstclk is pulled low, the pvr may read 0x000802b_. l2tstclk should be pulled up for normal operation.
dd 2.x powerpc 750fx risc microprocessor preliminary 1. general information page 6 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 1.4 part number information figure 1-1. part number legend ibm25ppc750fx-gb powerpc 750 family member process technology test conditions shipping container reliability grade performance sort package type design revision level note: see the datasheet supplement for additional application conditions. process technology ?= 0.13 m csoi design revision level d = dd2.0 e = dd2.1 f = dd2.2 g = dd2.3 package type b = ceramic ball grid array performance sort 01 = nominal at 600 mhz 05 = nominal at 700 mhz 10 = nominal at 733 mhz 25 = nominal at 800 mhz test conditions 1 = (see datasheet supplement and pcn-ibm-050803 2 = special test conditions 3 = 1.4 - 1.5v @ 105 c reliability grade 3 = grade 3, <100 fit afr 2 = grade 2, < 25 fit afr shipping container t = tray yy x 3 t
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 2. overview page 7 of 63 2. overview the powerpc 750fx risc microprocessor, also called the 750fx, is targeted for high performance, low power systems using a 60x bus. the 750fx also includes an internal 512kb l2 cache with on-board error correction circuitry (ecc). 2.1 block diagram figure 2-1 shows a block diagram of the powerpc 750fx risc microprocessor. figure 2-1. powerpc 750fx risc microprocessor block diagram gprs lsu fpu instruction fetch system completion rename buffers unit 32kb i-cache bht / enhanced l2 cache fxu2 dispatch branch unit btic control unit fprs rename buffers 512kb 32kb d-cache l2 tags fxu1 w/ecc 60x biu with parity with parity with parity
dd 2.x powerpc 750fx risc microprocessor preliminary 2. overview page 8 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 2.2 general parameters table 2-1 provides a summary of the general parameters of the 750fx. table 2-1. 750fx general parameters item description notes technology 0.13 m csoi technology, six-layer metallization plus one level of local interconnect die size 34.3 sq. mm transistor count 38 million - including l2 cache logic design fully-static package 292-pin ceramic ball grid array (cbga) 21x21mm (1.0 mm pitch) 0.8 mm ball size core power supply 1.45v +/- 50 mv 1 i/o power supply 3.3v +/- 165mv (bvsel = 1, l1_tstclk = 0) or 2.5v +/- 125mv (bvsel = 1, l1_tstclk = 1) or 1.8v +/- 100mv (bvsel = 0, l1_tstclk = 1) 2 note: 1. in some cases, when using 1.8v or 2.5v io mode, it is possible to reduce power dissipation by lowering the core power supply volt- age. see the datasheet supplement for details. 2. bvsel =0, l1_tstclk = 0 is an invalid setting. dd2.0 supports only a limited use of 3.3v io mode. see the 750fx errata list for revision dd2.x for more information.
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 3. electrical and thermal characteristics page 9 of 63 3. electrical and thermal characteristics this section provides ac and dc electrical specifications and thermal characteristics for the 750fx. 3.1 dc electrical characteristics the tables in this section describe the dc electrical characteristics for the 750fx. table 3-1. absolute maximum ratings 1 characteristic symbol 1.8v 2.5v 3.3v unit notes core supply voltage v dd -0.3 to 1.6 -0.3 to 1.6 -0.3 to 1.6 v 3, 4 pll supply voltage a1v dd , a2v dd -0.3 to 1.6 -0.3 to 1.6 -0.3 to 1.6 v 3, 4, 5 60x bus supply voltage ov dd -0.3 to 2.0 -0.3 to 2.75 -0.3 to 3.7 v 3, 4 input voltage v in -0.3 to 2.0 -0.3 to 2.75 -0.3 to 3.7 v 2 storage temperature range t stg -55 to 150 -55 to 150 -55 to 150 c notes: 1. functional and tested operating conditions are given in table 3-2, ?ecommended operating conditions on page 10. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed above may affect device reliability or cause permanent damage to the device. 2. caution: transient v in overshoots of up to ov dd + 0.8v, with a maximum of 4.0v for 3.3v operation, and undershoots down to gnd - 0.8v, are allowed for up to 5ns. 3. caution: ov dd must not exceed v dd /av dd by more than 2.1v continuously. ov dd may exceed v dd /av dd by up to 2.3v for up to 20ms during power-on or power-off. ov dd must not exceed v dd /av dd by more than 2.3v for any amount of time. 4. caution: v dd /av dd must not exceed ov dd by more than 1.0v continuously. v dd /av dd may exceed ov dd by up to 1.6v for up to 20ms during power-on or power-off. v dd /av dd must not exceed ov dd by more than 1.6v for any amount of time. 5. caution: av dd must not exceed v dd by more than 0.5v at any time.
dd 2.x powerpc 750fx risc microprocessor preliminary 3. electrical and thermal characteristics page 10 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 note: all electrical specifications (ac, dc, timing) are guaranteed only while the device is operated within the recommended operating conditions (see table 3-2 ). operation at other application conditions may also be possible; see the powerpc 750fx risc microprocessor datasheet supplement for details. table 3-2. recommended operating conditions characteristic symbol value unit notes core supply voltage (full-on mode) v dd 1.4 to 1.5 v 1, 2 low voltage (low frequency operation, 1.8v and 2.5v bus modes only) v dd 1.2 minimum v 1 pll supply voltage av dd 1.4 to 1.5 v 2 60x bus supply voltage (1.8v) ov dd 1.7 to 1.9 v 2 60x bus supply voltage (2.5v) ov dd 2.375 to 2.625 v 2 60x bus supply voltage (3.3v) ov dd 3.135 to 3.465 v input voltage v in gnd to ov dd v2 die-junction temperature dd2.0 and 2.1 t j 0 to 105 c die-junction temperature dd2.2 and 2.3 t j -40 to 105 notes: 1. in some cases, when using 1.8v or 2.5v io mode, it is possible to reduce power dissipation by lowering the core power supply volt- age. see the datasheet supplement for details. 2. these are tested operating conditions. table 3-3. package thermal characteristics 1 characteristic symbol 2 value unit cbga package thermal resistance, junction-to-case thermal resistance (typical) jc 0.06 c/w cbga package thermal resistance, junction-to-lead thermal resistance (typical) jb 7.6 c/w notes: 1. a heat sink is required (see section 5.8 thermal management on page 49). 2. jc is the internal resistance from the junction to the back of the die. for more information about thermal management, see section 5.8 thermal management on page 49.
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 3. electrical and thermal characteristics page 11 of 63 table 3-4. dc electrical speci?ations see table 3-2 on page 10 for recommended operating conditions. characteristic symbol voltage unit notes min max input high voltage (all inputs except sysclk) v ih (1.8v) 1.20 v v ih(2.5v) 1.70 v v ih(3.3v) 2.1 v input low voltage (all inputs except sysclk) v il(1.8v ) 0.60 v v il(2.5v) 0.70 v v il(3.3v) 0.80 v sysclk input high voltage cv ih(1.8v) 1.20 v cv ih(2.5v) 1.90 v cv ih(3.3v) 2.1 v sysclk input low voltage cv il(1.8v) 0.40 v input leakage current, v in = applies to all ov dd levels i in 20 a2 hi-z (off state) leakage current, v in = applies to all ov dd levels i tsi 20 a2 output high voltage, i oh = ?ma v oh(1.8v) 1.30 v v oh(2.5v) 2.00 v v oh(3.3v) 2.40 v output low voltage, i ol = 4ma v ol(1.8v, 2.5v, 3.3v) 0.4 v capacitance, v in =0 v, f = 1mhz c in 5pf1 notes: 1. capacitance values are guaranteed by design and characterization, and are not tested . 2. additional input current may be attributed to the level protection keeper lock circuitry. for details, see section 5.5 level protection on page 48.
dd 2.x powerpc 750fx risc microprocessor preliminary 3. electrical and thermal characteristics page 12 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 previous revisions of this datasheet showed incorrectly low power dissipation values. the power dissipation of the 750fx has not increased, the datasheet has only been corrected to show the actual values. table 3-5. power consumption see table 3-2 on page 10 for recommended operating conditions. mode v dd t j representative processor frequency (see note 6) unit notes 400 mhz 600 mhz 700 mhz 733 mhz 800 mhz full-on mode maximum 1.45v 105?c 7.1 7.9 8.2 8.3 8.6 1, 2 1.5v 105?c 7.9 8.7 9.3 9.4 9.7 1, 2 typical 1.45v 85?c 3.9 4.6 5.0 5.1 5.4 1, 3 nap mode typical 1.45v 50?c 1.4 1.5 1.6 1.6 1.6 w 1 sleep mode typical 1.45v 50?c 1.4 1.4 1.4 1.4 1.4 w 1 notes: 1. these values apply for all valid 60x buses. the values do not include i/o supply power (ov dd ) or pll/dll supply power (av dd ). ov dd power is sys- tem dependent, but is typically <2% of v dd power. av dd current is less than 25ma each for av dd1 and av dd2 . 2. maximum power is specified for fastest (worst process) parts running rc5 at the indicated core voltage, junction temperature, and core frequency. 3. typical power is specified for median process 800 mhz parts0 running rc5 at the indicated core voltage, junction temperature, and core frequency. the value is then adjusted for 13% less switching (ac component for p d ) to account for the differences between rc5 and more typical application code.
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 3. electrical and thermal characteristics page 13 of 63 3.2 clock ac speci?ations table 3-6 provides the clock ac timing specifications as defined in figure 3-1. table 3-6. clock ac timing speci?ations (see table 3-2 on page 10 for recommended operating conditions 1,6 ) num (timing reference) characteristic value unit notes min. max. processor frequency 400 800 mhz 7 sysclk frequency 20 200 mhz 1, 6 1 sysclk cycle time 5.0 50 ns 2, 3 sysclk rise and fall slew rate 1.0 v/ns 3 4 sysclk duty cycle measured at 0.8v 25 75 % 3 vm sysclk measurement reference voltage for sysclk (all i/o voltages) 0.65 v sysclk cycle-to-cycle jitter 150 ps 4, 3 internal pll relock time 100 s5 notes: 1. caution: the sysclk frequency and the pll_cfg[0:4] settings must be chosen such that the resulting sysclk (bus) frequency, cpu (core) frequency, and pll frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:4] signal description in table 5-2, ?50fx microprocessor pll configuration?on page 33 for valid pll_cfg[0:4] settings. 2. the sysclk slew rate applies between 0.4v and 1.0v. 3. timing is guaranteed by design and characterization, and is not tested. 4. see section 3.3 spread spectrum clock generator (sscg) on page 14 for long term jitter. 5. relock timing is guaranteed by design and characterization, and is not tested. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on reset sequence. this speci?ation also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. 6. this is a statement of the capability of the 750fx i/o circuitry. not all systems can run at the maximum sysclk frequency. co n- tact ibm powerpc application engineering for more information on high-speed bus design. 7. lower voltage/frequency operation: for additional information, see 750fx datasheet supplement for dd2.x revisions . figure 3-1. sysclk input timing diagram vm cv il cv ih 1 2 4 3 4 sysclk vm sysclk - midpoint voltage for sysclk
dd 2.x powerpc 750fx risc microprocessor preliminary 3. electrical and thermal characteristics page 14 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 3.3 spread spectrum clock generator (sscg) when designing with the sscg, there are a number of design issues that must be taken into account. sscg creates a controlled amount of long-term jitter. in order for a receiving pll in the 750fx to operate in this environment, it must be able to accurately track the sscg clock jitter. the accuracy to which the 750fx pll can track the sscg clock is referred to as tracking skew. when performing system timing analysis, the tracking skew must be added or subtracted to the i/o timing specifica- tions because the tracking skew appears as a static phase error between the internal pll and the sscg clock. to minimize the impact on i/o timings the following sscg configuration is recommended: the following sscg configuration is recommended: - down spread mode, less than or equal to 1% of the maximum frequency - a modulation frequency of 30khz - linear sweep modulation or ?ershey kiss ? 1 (as in a lexmark2 pro?e) modulation pro?e as shown in figure 3-2 on page 14. in this configuration the tracking skew is less than 100ps. 1. hershey kiss is a trademark of hershey foods corporation. 2. see patent 5,631,920. figure 3-2. linear sweep modulation pro?e down spread frequency change 0% -1% 0 s time increases percentage decreases 33.3 s
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 3. electrical and thermal characteristics page 15 of 63 3.4 60x bus input ac speci?ations figure 3-3 provides the input timing diagram for the 750fx. table 3-7. 60x bus input timing speci?ations see table 3-2 on page 10 for operating conditions. 1,5 num characteristic 1.8v mode 2.5v mode 3.3v mode unit notes min. max. min. max. min. max. 10a all inputs valid to sysclk (input setup) 1.0 1.5 1.8 ns 10b int_, smi_, mcp, tben, drtry, and tlbisync (input setup) 1.5 1.5 1.8 10c mode select input setup to hreset ( tlbisync, drtry) 8??t sysclk 2, 3, 4, 5 11a sysclk to inputs invalid (input hold) 0.65 0.65 0.55 ns 6 11b int_, smi_, mcp, tben, drtry, and tlbisync (input hold) 1.5 2.5 2.5 ns 11c hreset to mode select input hold ( tlbisync, drtry) 0 0 0 ns 2, 4, 5 vm measurement reference voltage for inputs ov dd /2 notes: 1. input specifications are measured from the vm of the signal in question to vm of the rising edge of the input sysclk. input a nd output timings are measured at the pin (see figure 3-3). 2. the setup and hold time is with respect to the rising edge of hreset (see figure 3-4 on page 16). 3. t sysclk , is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in ns) of the parameter in question. 4. this speci?ation is for con?uration mode select only. also note that the hreset must be held asserted for a minimum of 255 bus clocks after the pll relock time during the power-on reset sequence. 5. all values are guaranteed by design, and are not tested. 6. see alternate i/o timing for 3.3v bus on page 19 figure 3-3. input timing diagram vmsysclk(0.65v) sysclk all inputs vm = midpoint voltage (ov dd /2) 10b 10a 11a vm vm 11b
dd 2.x powerpc 750fx risc microprocessor preliminary 3. electrical and thermal characteristics page 16 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 figure 3-4 provides the mode select input timing diagram for the 750fx. figure 3-4. mode select input timing diagram v ih v ih = 1.20v for 1.8v o v dd mode pins 10c 11c hreset 10c 11c v ih = 1.70v for 2.5v o v dd v ih = 2.1v for 3.3v o v dd
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 3. electrical and thermal characteristics page 17 of 63 3.5 60x bus output ac speci?ations table 3-8 provides the 60x bus output ac timing specifications for the 750fx as defined in figure 3-6 on page 19. table 3-8. 60x bus output ac timing speci?ations see table 3-2 on page 10 for operating conditions. 1, 5 num characteristic 1.8v 2.5v 3.3v unit notes min. max. min. max. min. max. 12 sysclk to output driven (output enable time) 0.3 0.3 0.3 ns 13 sysclk to output valid 2.3 2.5 2.5 ns 2, 6 14 sysclk to output invalid (output hold) 0.5 0.55 0.55 ns 2, 7 15 sysclk to output high impedance (all signals except artry, abb and dbb) 2.5 2.5 2.5 ns 16 sysclk to abb and dbb high impedance after precharge 1.0 1.0 1.0 t sysclk 3, 4 17 sysclk to artry high impedance before precharge 3.0 3.0 3.0 ns 18 sysclk to artry precharge enable 0.2 t sysclk + 1.0 0.2 t sysclk + 1.0 0.2 t sysclk + 1.0 ns 2, 3, 4 19 maximum delay to artry precharge 1.0 1.0 1.0 t sysclk 3, 4 20 sysclk to artry high impedance after precharge 2.0 2.0 2.0 t sysclk 3, 4 notes: 1. all output specifications are measured from the vm of the rising edge of sysclk to the output signal level defined in figure 3-5 on page 18. both input and output timings are measured at the pin. timings are determined by design. 2. this minimum parameter assumes cl = 0pf. 3. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration of the parameter in question. 4. nominal precharge width for ar tr y is 1.0 t sysclk . 5. guaranteed by design and characterization, and not tested. 6. output valid timing increases as the v dd in reduced. these values assumes v dd minimum of 1.35v. 7. see alternate i/o timing for 3.3v bus on page 19
dd 2.x powerpc 750fx risc microprocessor preliminary 3. electrical and thermal characteristics page 18 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 figure 3-5. output valid timing de?ition note: the timing definition uses an infinitely long transmission line model. 65 ohm line output driver sysclk positive output transition negative output transition 1/4 ov dd 3/4 ov dd output transition de?ned between sysclk @ vm and the respective transition level. vm
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 3. electrical and thermal characteristics page 19 of 63 3.6 alternate i/o timing for 3.3v bus an alternate i/o timing specification may be used for dd2.3, where: ?v dd = 3.3v +/- 5%, ? dd = 1.45v +/- 50mv, and ? j = -40 0 c to 105 0 c. all other recommended operating conditions are as per table 3-2. the following alternate i/o timing specifications may be used under the above conditions: 1. consider v m = 1/2 (ov dd ) for sysclk, input timing, and output timings. 2. input hold (t11a) becomes 250 ns minimum for 3.3v. output hold (t14) becomes 650 ns minimum for 3.3v. 3. all other timing speci?ations are unchanged. figure 3-6. output timing diagram for powerpc 750fx risc microprocessor note: sysclk vm as defined in section 3.2 clock ac specifications on page 13. output vm as defined in section 3-5 output valid timing definition on page 18. sysclk all outputs (except ts, artry) ts artry 12 13 13 14 15 15 vm sysclk vm sysclk 14 vm sysclk 13 19 17 20 18 vm vm vm low level hi-z high level 16 abb, dbb
dd 2.x powerpc 750fx risc microprocessor preliminary 3. electrical and thermal characteristics page 20 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 3.6.1 ieee 1149.1 ac timing speci?ations the five jtag signals are; tdi, tdo, tms, tck, and trst. unless otherwise noted, jtag specifications are referenced to gnd and ov dd . the jtag i/os are powered by ov dd . table 3-9. jtag ac timing speci?ations (independent of sysclk) see table 3-2 on page 10 for operating conditions. num characteristic min. max. unit notes tck frequency of operation 0 25 mhz 1 tck cycle time 40 ns 2 tck clock pulse width measured at 1.1v 15 ns 3 tck rise and fall times 0 2 ns 4 4 specification obsolete, intentionally omitted 5 trst assert time 25 ns 1 6 boundary-scan input data setup time 0 ns 2 7 boundary-scan input data hold time 13 ns 2 8 tck to output data valid 8 ns 3, 5 9 tck to output high impedance 3 19 ns 3, 4 10 tms, tdi data setup time 0 ns 11 tms, tdi data hold time 15 ns 12 tck to tdo data valid 2.0 12 ns 5 13 tck to tdo high impedance 3 9 ns 4 14 tck to output data invalid (output hold) 0 ns notes: 1. trst is an asynchronous level sensitive signal. guaranteed by design. 2. non-jtag signal input timing with respect to tck. 3. non-jtag signal output timing with respect to tck. 4. guaranteed by characterization and not tested. 5. minimum speci?ation guaranteed by characterization and not tested. figure 3-7. jtag clock input timing diagram 1 2 2 3 3 vm tck vm vm vm = midpoint voltage (ov dd /2)
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 3. electrical and thermal characteristics page 21 of 63 figure 3-8. trst timing diagram figure 3-9. boundary-scan timing diagram figure 3-10. test access port timing diagram 5 trst 9 6 7 8 9 tck data inputs data outputs data outputs input data valid output data valid 12 10 11 tck tdi, tms tdo tdo input data (valid) output data (valid) tdo 13 14 output data (invalid)
dd 2.x powerpc 750fx risc microprocessor preliminary 4. dimensions and signal assignments page 22 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 4. dimensions and signal assignments ibm offers a ceramic ball grid array (cbga) which supports 292 balls for the 750fx package. 4.1 module substrate decoupling voltage assignments the on-board substrate voltage-to-ground assignments for the capacitor locations are shown in figure 4-1 . 4.2 package module mass is approximately 3.25 grams. ball pitch is 1 mm. ball diameter target is 0.8 mm +/- 0.04 mm. jedec moisture sensitivity level is 1. for pad, line, via, and dogbone recommendations, ask for ?rinted wiring board tech for 1.0 mm pitch modules. note: use a01 corner designation for correct placement. use the five plated dots that form a right angle (|_) to locate the a01 corner as shown in figure 4-2 mechanical dimensions and bottom surface nomenclature of the cbga package on page 23. figure 4-1. module substrate decoupling voltage assignments a01 47p6892 corner gnd v dd ov dd gnd gnd v dd ov dd gnd v dd gnd gnd ov dd gnd ov dd
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 4. dimensions and signal assignments page 23 of 63 figure 4-2. mechanical dimensions and bottom surface nomenclature of the cbga package t notes: 4. dimensioning and tolerancing per asme y14.5m, 1994. 5. dimensions in millimeters. millimeters dim minimum maximum a 21 0.2 a1 7.03 a2 1.5 b 21 0.2 b1 5.32 c 1.5 c1 0.48 c2 0.51 d 2.5 f 2.569 3.087 f1 1.859 2.177 g 0.779 0.857 g1 (7x) 0.20 0.51 h1.79 2.23 h1 1.08 1.32 h2 0.71 0.91 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 u v wa b c d e f g h j k l m n p r not to scale note: all caps on the scm are lower in height than the processor die. 20 y f1 f g g1 h h1 h2 b c 292x a 0.3 c 0.1 b a b b1 a1 a2 a01 c1 c2 c (19x) (19x) d 47p6892 (bottom side view) 1 1 a01 corner corner
dd 2.x powerpc 750fx risc microprocessor preliminary 4. dimensions and signal assignments page 24 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 4.3 microprocessor ball placement figure 4-3. powerpc 750fx microprocessor ball placement 20 a6 a8 a3 a2 a0 dh31 dh25 dh26 dp2 dh22 dh19 dh18 dh16 dh15 dh14 dp0 dh9 dh10 dh4 dh2 19 a13 gnd a5 a4 a1 dh29 dp3 dh28 dh23 dh24 dh21 dh20 dp1 dh17 dh11 dh8 dh6 dh5 gnd dh3 18 a11 a10 ovdd gnd ovdd gnd vdd vdd gnd ovdd gnd ovdd dh0 pll_cfg0 17 a12 tt1 ovdd a9 dh30 dh27 gnd gnd dh12 dh13 dh1 ovdd pll_cfg1 pll_cfg2 16 a14 a15 gnd ap0 a7 gnd ovdd ovdd ovdd ovdd gnd dh7 pll_cfg3 gnd sysclk a2vdd 15 tt3 ts vdd vdd pll_rng0 a1vdd 14 tsiz0 tt2 ovdd tt0 gnd ovdd gnd gnd ovdd gnd pll_rng1 ovdd pll_cfg4 agnd 13 ap2 tt4 gnd ap1 vdd gnd gnd vdd vdd vdd vdd gnd gnd vdd llsd_ mode gnd l2_tstclk l1_tstclk 12 ta tsiz1 vdd gnd gnd gnd gnd vdd mcp checkstop 11 tbst tsiz2 vdd gnd ovdd gnd vdd vdd gnd ovdd gnd vdd tlbisync hreset 10 dbdis a16 vdd gnd ovdd gnd gnd gnd gnd ovdd gnd vdd smi ckstp 9 a18 a17 vdd gnd vdd vdd gnd vdd bvsel int 8 aack ap3 gnd a21 vdd gnd gnd vdd vdd vdd vdd gnd gnd vdd qreq gnd tben qack 7 a20 a19 ovdd a24 gnd ovdd gnd gnd ovdd gnd dbb ovdd artry sreset 6 dbwo a23 vdd vdd tea abb 5 a22 a26 gnd a25 a31 gnd ovdd ovdd ovdd ovdd gnd clk_o ut wt gnd tdo dbg 4 a28 a27 ovdd dl3 dp5 dl13 gnd gnd dl23 dl26 ci ovdd bg rsrv 3 a29 a30 ovdd gnd ovdd gnd vdd vdd gnd ovdd gnd ovdd drtry br 2 dl0 gnd dl2 dl6 dl5 dl11 dl10 dl12 dl16 dl15 dl19 dl20 dl22 dl27 dl28 tck dl30 tdi gnd blank 1 dl1 dp4 dl4 dl8 dl7 dl9 dl14 dp6 dl18 dl17 dl21 dp7 dl24 dl25 dl29 dl31 trst tms gbl blank a b c d e f g h j k l m n p r t u v w y note: this view is looking down from above the 750fx placed and soldered on the system board.
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 4. dimensions and signal assignments page 25 of 63 4.4 pinout listings table 4-1 contains the pinout listing for the 750fx cbga package. table 4-1. pinout listing for the cbga package signal name pin number active input/output notes a[0:31] e20, e19, d20, c20, d19, c19, a20, e16, b20, e17, b18, a18, a17, a19, a16, b16, b10, b9, a9, b7, a7, d8, a5, b6, d7, d5, b5, b4, a4, a3, b3, e5. high input/output a1vdd y15 a2vdd y16 aack a8 low input abb y6 low input/output agnd y14 ap[0:3] d16, d13, a13, b8 high input/output 6 artry w7 low input/output bg w4 low input blank y1, y2 3 br y3 low output bvsel w9 input 4 checkstop (ckstp_out) y12 low output ci t4 low output ckstp_in y10 low input clk_out t5 high output dbb u7 low input/output dbdis a10 low input dbg y5 low input dbwo a6 low input dh[0:31] w18, t17, y20, y19, w20, v19, u19, t16, t19, u20, v20, r19, n17, p17, r20, p20, n20, p19, m20, l20, m19, l19, k20, j19, k19, g20, h20, h17, h19, f19, g17, f20 high input/output dl[0:31] a2, a1, c2, e4, c1, e2, d2, e1, d1, f1, g2, f2, h2, h4, g1, k2, j2, k1, j1, l2, m2, l1, n2, n4, n1, p1, p4, p2, r2, r1, u2, t1 high input/output dp[0:7] t20, n19, j20, g19, b1, g4, h1, m1 high input/output 6 drtry w3 low input gbl w1 low input/output notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the input/output drivers and v dd inputs supply power to the processor core. 3. these pins are reserved for potential future use. 4. bvsel and l1_tstclk select the input/output voltage mode on the 60x bus (see section 5.7 on page 49). 5. tck must be tied high or low for normal machine operation. 6. address and data parity should be left ?ating if unused in the design.
dd 2.x powerpc 750fx risc microprocessor preliminary 4. dimensions and signal assignments page 26 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 gnd b2, b19, c5, c8, c13, c16, d10, d11, e3, e7, e14, e18, f10, f11, g5, g8, g13, g16, h3, h8, h9, h12, h13, h18, j12, k4, k7, k10, k14, k17, l4, l7, l10, l14, l17, m12, n3, n8, n9, n12, n13, n18, p5, p8. p13, p16, r10, r11, t3, t7, t14, t18, u10, u11, v5, v8, v13,v16, w2, w19, hreset y11 low input int y9 low input l1_tstclk y13 high input 4 l2_tstclk w13 high see note 1. input 1 lssd_mode u13 low input 1 mcp w12 low input ov dd c4, c7, c14, c17, d3, d18, e10, e11, g3, g7, g14, g18, h5, h16, k5, k16, l5, l16, n5, n16, p3, p7, p14, p18, t10, t11, u3, u18, v4, v7, v14, v17 2 pll_cfg[0:4] y18, w17, y17, u16, w14 high input pll_rng[0:1] w15, u14 high input qack y8 low input qreq u8 low output rsrv y4 low output smi w10 low input sreset y7 low input sysclk w16 high input ta a12 low input tben w8 high input tbst a11 low input/output tck t2 high input 5 tdi v2 high input tdo w5 high output tea w6 low input tlbisync w11 low input tms v1 high input trst u1 low input ts b15 low input/output table 4-1. pinout listing for the cbga package (continued) signal name pin number active input/output notes notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the input/output drivers and v dd inputs supply power to the processor core. 3. these pins are reserved for potential future use. 4. bvsel and l1_tstclk select the input/output voltage mode on the 60x bus (see section 5.7 on page 49). 5. tck must be tied high or low for normal machine operation. 6. address and data parity should be left ?ating if unused in the design.
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 4. dimensions and signal assignments page 27 of 63 tsiz[0:2] a14, b12, b11 high output tt[0:4] d14, b17, b14, a15, b13 high input/output v dd c10, c11, e8, e13, f6, f9, f12, f15, j8, j9, j13, k3, k8, k11, k13, k18, l3, l8, l11, l13, l18, m8, m9, m13, r6, r9, r12, r15, t8, t13, v10, v11 2 wt u5 low output table 4-1. pinout listing for the cbga package (continued) signal name pin number active input/output notes notes: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the input/output drivers and v dd inputs supply power to the processor core. 3. these pins are reserved for potential future use. 4. bvsel and l1_tstclk select the input/output voltage mode on the 60x bus (see section 5.7 on page 49). 5. tck must be tied high or low for normal machine operation. 6. address and data parity should be left ?ating if unused in the design.
dd 2.x powerpc 750fx risc microprocessor preliminary 4. dimensions and signal assignments page 28 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 . table 4-2. signal locations signal ball location signal ball location signal ball location signal ball location a0 e20 dh0 w18 dl0 a2 aack a8 a1 e19 dh1 t17 dl1 a1 abb y6 a2 d20 dh2 y20 dl2 c2 agnd y14 a3 c20 dh3 y19 dl3 e4 artry w7 a4 d19 dh4 w20 dl4 c1 bg w4 a5 c19 dh5 v19 dl5 e2 br y3 a6 a20 dh6 u19 dl6 d2 bvsel w9 a7 e16 dh7 t16 dl7 e1 checkstop ( ckstp_out) y12 a8 b20 dh8 t19 dl8 d1 ci t4 a9 e17 dh9 u20 dl9 f1 clk_out t5 a10 b18 dh10 v20 dl10 g2 ckstp ( ckstp_in) y10 a11 a18 dh11 r19 dl11 f2 dbb u7 a12 a17 dh12 n17 dl12 h2 dbdis a10 a13 a19 dh13 p17 dl13 h4 dbg y5 a14 a16 dh14 r20 dl14 g1 dbwo a6 a15 b16 dh15 p20 dl15 k2 drtry w3 a16 b10 dh16 n20 dl16 j2 gbl w1 a17 b9 dh17 p19 dl17 k1 hreset y11 a18 a9 dh18 m20 dl18 j1 int y9 a19 b7 dh19 l20 dl19 l2 l1_tstclk y13 a20 a7 dh20 m19 dl20 m2 l2_tstclk w13 a21 d8 dh21 l19 dl21 l1 lssd_mode u13 a22 a5 dh22 k20 dl22 n2 mcp w12 a23 b6 dh23 j19 dl23 n4 pll_cfg0 y18 a24 d7 dh24 k19 dl24 n1 pll_cfg1 w17 a25 d5 dh25 g20 dl25 p1 pll_cfg2 y17 a26 b5 dh26 h20 dl26 p4 pll_cfg3 u16 a27 b4 dh27 h17 dl27 p2 pll_cfg4 w14 a28 a4 dh28 h19 dl28 r2 pll_rng0 w15 a29 a3 dh29 f19 dl29 r1 pll_rng1 u14 a30 b3 dh30 g17 dl30 u2 qack y8 a31 e5 dh31 f20 dl31 t1 qreq u8 rsrv y4 smi w10 sreset y7 sysclk w16
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 4. dimensions and signal assignments page 29 of 63 ap0 d16 dp0 t20 ta a12 ap1 d13 dp1 n19 tben w8 ap2 a13 dp2 j20 tbst a11 ap3 b8 dp3 g19 tck t2 dp4 b1 tdi v2 dp5 g4 tdo w5 dp6 h1 tea w6 dp7 m1 tlbisync w11 tms v1 trst u1 ts b15 tsiz0 a14 tsiz1 b12 tsiz2 b11 tt0 d14 tt1 b17 tt2 b14 tt3 a15 tt4 b13 wt u5 table 4-2. signal locations (continued) signal ball location signal ball location signal ball location signal ball location
dd 2.x powerpc 750fx risc microprocessor preliminary 4. dimensions and signal assignments page 30 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 table 4-3. voltage and ground assignments a1v dd a2v dd ov dd ov dd v dd v dd gnd gnd y15 y16 c4 c7 c10 c11 b2 b19 c14 c17 e8 e13 c5 c8 d3 d18 f6 f9 c13 c16 e10 e11 f12 f15 d10 d11 g3 g7 j8 j9 e3 e7 g14 g18 j13 k3 e14 e18 h5 h16 k8 k11 f10 f11 k5 k16 k13 k18 g5 g8 l5 l16 l3 l8 g13 g16 n5 n16 l11 l13 h3 h8 p3 p7 l18 m8 h9 h12 p14 p18 m9 m13 h13 h18 t10 t11 r6 r9 j12 k4 u3 u18 r12 r15 k7 k10 v4 v7 t8 t13 k14 k17 v14 v17 v10 v11 l4 l7 l10 l14 l17 m12 n3 n8 n9 n12 n13 n18 p5 p8 p13 p16 r10 r11 t3 t7 t14 t18 u10 u11 v5 v8 v13 v16 w2 w19
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 31 of 63 5. system design information this section provides electrical and thermal design recommendations for successful application of the 750fx. for more information, see the powerpc faq, the powerpc 750fx errata list, any applicable pcns, and the other powerpc documentation and application notes in the powerpc technical library on our web site. 5.1 pll considerations the 750fx design includes two plls (pll0 and pll1), allowing the processor clock frequency to dynami- cally change between the pll frequencies via software control. use the bits in the hid1 register to specify: 1. the frequency range of each pll 2. the clock multiplier for each pll 3. external or internal control of pll0 4. the selected pll (which is the source of the processor clock at any given time) for hid1 bit definitions, see the powerpc 750 fx user? manual . note: the pll configuration must adhere to the supported frequency range as specified in this document and in the ibm 750fx datasheet supplement for dd2.x product revisions , for the minimum v dd condition. voltages (v dd /av dd ) should remain constant at all times. at power-on reset, the hid1 register contains zeroes for all the non-read-only bits (bits 7 to 31). this configu- ration corresponds to the selection of pll0 as the source of the processor clocks and selects the external configuration and range pins to control pll0. the external configuration and range pin values are accessible to software using hid1 read-only bits 0-6. pll1 is always controlled by its internal configuration and range bits. the hid1 setting associated with hard reset corresponds to a pll1 configuration of clock off, and selec- tion of the medium frequency range. hreset must be asserted during power up long enough for the pll(s) to lock, and for the internal hardware to be reset. once this timing is satisfied, hreset can be negated. the processor now will proceed to execute instructions, clocked by pll0 as configured via the external pins. the processor clock frequency can be modified from this initial setting in one of two ways. first, as with earlier designs, hreset can be asserted, and the external configuration pins can be set to a new value. the machine state is lost in this process, and, as always, hreset must be held asserted while the pll relocks, and the internal state is reset. second, the introduction of another pll provides an alternative means of changing the processor clock frequency, which does not involve the loss of machine state nor a delay for pll relock. the following sequence can be used to change processor clock frequency. note: assume pll0 is currently the source for the processor clock. 1. con?ure pll1 to produce the desired clock frequency by setting hid1[pr1] and hid1[pc1] to the appropriate values. 2. wait for pll1 to lock. the lock time is the same for both plls and is provided in the hardware speci?a- tion. 3. set hid1[ps] to 1 to initiate the transition from pll0 to pll1 as the source of the processor clocks. from the time the hid1 register is updated to select the new pll, the transition to the new clock fre- quency will complete within three (3) bus cycles. after the transition, the hid(pss) bit indicates which pll is in use.
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 32 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 after both plls are running and locked, the processor frequency can be toggled with very low latency. for example, when it is time to change back to the pll0 frequency, there is no need to wait for pll lock. hid1[ps] can be reset to 0, causing the processor clock source to transition from pll1 back to pll0. if pll0 will not be needed for some time, it can be configured to be off while not in use. this is done by resetting the hid1[pc0] field to 0, and setting hid1[pi0] to 1. turning the non-selected pll off results in a modest power savings, but introduces added latency when changing frequency. if pll0 is configured to be off, the procedure for switching to pll0 as the selected pll involves changing the configuration and range bits, waiting for lock, and then selecting pll0, as described in the previous paragraph. 5.1.1 restrictions and considerations for pll con?uration avoid the following when reconfiguring the plls: 1. the con?uration and range bits in hid1 should only be modi?d for the non-selected pll, since it will require time to lock before it can be used as the source for the processor clock. 2. the hid1[pi0] bit should only be modi?d when pll0 is not selected. 3. whenever one of the plls is recon?ured, it must not be selected as the active pll until enough time has elapsed for the pll to lock. 4. at all times, the frequency of the processor clock, as determined by the various con?uration settings, must be within the speci?ation range for the current operating conditions. 5. never select a pll that is in the ?ff?con?uration. 5.1.1.1 con?uration restriction on frequency transitions it is considered a programming error to switch from one pll to the other when both are configured in a half-cycle multiplier mode. for example, with pll0 configured in 9:2 mode (cfg = 01001) and pll1 config- ured in 13:2 mode (cfg = 01101), changing the select bit (hid1[ps]) is not allowed. in cases where such a pairing of configurations is desired, an intermediate full-cycle configuration must be used between the two half-cycle modes. for example, with pll0 at 9:2, pll1, configured at 6:1 is selected, then pll0 is reconfig- ured at 13:2, locked and selected. 5.1.2 pll_rng[0:1] de?itions for dual pll operation the dual plls on the 750fx are configured by the pll_cfg[0:4] and pll_rng[0:1] signals. for a given sysclk (bus) frequency, the pll configuration signals set the internal cpu and vco frequency of opera- tion. the pll range configuration, for dual pll operation, for the 750fx is shown in the following table. table 5-1. pll_rng [0:1] de?itions for dual pll operation pll_rng[0:1] pll frequency range 00 600 mhz and above 10 below 600 mhz 01 reserved 11 reserved
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 33 of 63 5.1.3 pll con?uration pll-cfg ( table 5-2 ) must be set so that both sysclk and the core frequency are within the clock ac timing specifications shown in table 3-6 on page 13. in addition, the core frequency must not exceed the limit specified in the part number, and the system must meet the required specifications. table 5-2. 750fx microprocessor pll con?uration pll_cfg [0:4] processor to bus frequency ratio (pbfr) binary decimal 00000 0 off 00001 1 off 00010 2 pll bypass 2 00011 3 pll bypass 2 00100 4 2x 1 00101 5 2.5x 1 00110 6 3x 00111 7 3.5x 01000 8 4x 01001 9 4.5x 01010 10 5x 01011 11 5.5x 01100 12 6x 01101 13 6.5x 01110 14 7x 01111 15 7.5x 10000 16 8x 10001 17 8.5x 10010 18 9x 10011 19 9.5x 10100 20 10x 10101 21 11x 10110 22 12x 10111 23 13x 11000 24 14x 11001 25 15x 11010 26 16x notes: 1. the 2x- 2.5x processor to bus ratios are currently not supported. 2. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. the ac timing speci?ations given in the document do not apply in pll-bypass mode. 3. in clock-off mode, no clocking occurs inside the 750fx regardless of the sysclk input.
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 34 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 11011 27 17x 11100 28 18x 11101 29 19x 11110 30 20x 11111 31 off 3 table 5-2. 750fx microprocessor pll con?uration (continued) pll_cfg [0:4] processor to bus frequency ratio (pbfr) binary decimal notes: 1. the 2x- 2.5x processor to bus ratios are currently not supported. 2. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. the ac timing speci?ations given in the document do not apply in pll-bypass mode. 3. in clock-off mode, no clocking occurs inside the 750fx regardless of the sysclk input.
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 35 of 63 5.2 pll power supply filtering the 750fx microprocessor has two separate av dd signals (a1v dd and a2v dd ) which provide power to the clock generation phase-locked loops. most designs are expected to utilize a single pll configuration mode throughout the application. these type of designs should use the default, a1v dd (pll0) and tie the a2v dd (pll1) signal to ground (agnd) through a 100 ohm resistor. this is shown in figure 5-1 on page 36. for designs planning to optimize power savings through dynamic switching between these dual pll circuits, it is recommended, though not required, that each av dd have a separate voltage input and filter circuit. to ensure stability of the internal clock, the power supplied to the av dd input signals should be filtered using a circuit similar to the one shown in figure 5-1 on page 36. the circuit should be placed as close as possible to the av dd pin to ensure it filters out as much noise as possible. for descriptions of the sample pll power supply filtering circuits, see table 5-3 . table 5-3. sample pll power supply filtering circuits samples of pll power supply filtering circuits circuit description number of filtering circuits ferrite beads circuit figure recommended circuit design notes single pll circuit configuration that uses the a1v dd and ties the a2v dd pin to gnd. 11 figure 5-1 on page 36 yes single pll circuit configuration that uses both the a1v dd and the a2v dd pins and a single ferrite bead. 11 figure 5-2 on page 37 optional 1, 2 dual pll configuration that uses a separate circuit for the a1v dd pin and for the a2v dd the pin. 22 figure 5-3 on page 38 yes 2, 3 notes: 1. optional configurations are supported, though not recommended. 2. this circuit design can be used with the dual pll feature enabled, though optimum power savings may not be realized. for additional information, see figure 5-3 dual pll power supply filter circuits on page 38. 3. this circuit design can be used with the dual pll feature enabled to optimize power savings.
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 36 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 figure 5-1. single pll power supply filter circuit with a1v dd pin and a2v dd pin tied to gnd discrete resistor 2 ? ferrite bead1 av dd single pll (a1vdd) power supply filter circuit c2 c1 agnd pin 1 a1vdd pin legend: item description/value resistor 2 ? c1 0.1 f, ceramic c2 10.0 f, ceramic ferrite bead 30 ? (typical) - murata blm21p300s or similar note: 1. connected to ground without a ?ter. 2. single pll0 only. a2vdd 2 pin (recommended) discrete resistor 100 ? (v dd )
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 37 of 63 figure 5-2. pll power supply filter circuit with two av dd pins and one ferrite discrete resistor 2 ? ferrite bead1 single pll (a1vdd) power supply filter circuit c2 c1 agnd pin 1 a1vdd pin legend: item description/value resistor 2 ? c1 0.1 f ceramic c2 10.0 f ceramic ferrite bead 30 ? (typical) - murata blm21p300s or similar note: 1. connected to ground without a filter. a2vdd pin (optional) av dd (v dd )
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 38 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 figure 5-3. dual pll power supply filter circuits discrete resistor 2 ? ferrite bead dual pll (avdd) power supply filter circuits 1 2 c2 c1 agnd pin a1vdd pin item description/value resistor 2 ? c1 0.1 f ceramic c2 10.0 f ceramic ferrite bead 30 ? (typical) - murata blm21p300s or similar notes: 1. the dual pll power supply circuits shown in this figure are recommended for a design that uses the dual pll feature. for more information about the dual pll feature, see section 5.2 low voltage operation at lower frequency on page 40. 2. connected to ground without a ?ter. discrete resistor 2 ? ferrite bead 2 c2 c1 agnd pin a2vdd pin (recommended con?uration if dual pll feature is enabled.) av dd (v dd ) av dd (v dd )
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 39 of 63 5.3 decoupling recommendations capacitor decoupling is required for the 750fx. decoupling capacitors act to reduce high frequency chip switching noise and provide localized bulk charge storage to reduce major power surge effects. high frequency decoupling capacitors should be located as close as possible to the processor with low lead inductance to the ground and voltage planes. decoupling capacitors are recommended on the back of the card, directly opposite the module. the recom- mended placement and number of decoupling capacitors, 34 v dd -gnd caps and 44 ov dd -gnd caps are described in figure 5-4 orientation and layout of the 750fx decoupling capacitors . the recommended decoupling capacitor specifications are provided in table 5-4 recommended decoupling capacitor specifi- cations . the placement and usage described here are guidelines for decoupling capacitors and should be applied for system designs. the decoupling capacitor electrodes are located directly opposite from their corresponding bga pins where possible. also, each electrode for each decoupling capacitor needs to be connected to one or more bga pins (balls) with a short electrical path. thus, through-vias adjacent to the decoupling capacitors are recommended. the card designer can expand on the decoupling capacitor recommendations by doing the following: adding additional decoupling capacitors if using additional decoupling capacitors, verify that these additional capacitors do not reduce the number of card vias or cause the vias to lose proximity to each capacitor electrode. adding additional through-vias or blind-vias card technologies are available that will reduce the inductance between the decoupling capacitor and the bga pin (ball). replacing single vias with multiple vias is very effective. place gnd vias close to v dd or ov dd vias to reduce loop inductance. for more information on power layout and bypassing, see the ibm application note, ?owerpc 750fx layout and bypassing. table 5-4. recommended decoupling capacitor speci?ations item description decoupling capacitor speci?ations: type x5r or y5v 10v minimum 0402 size 40 x 20 mils, nominally 1.0 mm x 0.5 mm 0.1 mm on both dimensions 100 nf recommended minimum number of decou- pling capacitors on the back of the card: 34 v dd -gnd caps 44 ov dd -gnd caps
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 40 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 figure 5-4. 750fx pin locations: ov dd , v dd , gnd, and signal pins v v g g g g g g g g g g g g g g g g g g g g o g o g o o g o g o g o g o g o g o g o o g o g o g o o g o g o g o g o g o g g g g g o v v v g v v g g v g g v g v g v g v g g g v g v g v v o g o g o g o g o g o g g v g v g v g v g v g v g v v o g o g g g g g v v v v v v g o v v bottom view o y w v u t r p n m l k j h g f e d c b a 12 3 4 5 6 7 8 91011121314151617181920 = gnd pin = v dd pin = ov dd pin = signal pin g v o
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 41 of 63 figure 5-5. orientation and layout of the 750fx decoupling capacitors v v o g g g g g g g g g g g g g g g g g g g g g g g g g g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g o g g g g g o v v v g v v g g v g g v g v g v g v g g g v g v g v v o g o g o g o g o g o g g v g v g v g v g v g v g v v o g o g g g g g v g v v = av dd pin = agnd pin = ov dd gnd cap = v dd gnd cap = gnd via = v dd via = ov dd via = gnd pin = v dd pin = ov dd pin = signal pin g v o v g ov vd vg vg vg ov ov ov vg vd vd ov vg ov vg v v ov vg vg ov vg vg ov ov ov vg vg ov vd vg vd vg vd vg vg vd vd vd vd vg vg ov ov vg vd ov vg ov vg vg vg vg vd vd vd vd vg ov vg vg vg vg ov ov vg ov vd v vg vg ov vg ov vd vg ov v v g o vd vg vg vd ov vg vg vd vg vd vd vg vg vg ov ov ov vg vg vg ov ov vg vd ov v v bottom view ov vg vd y w v u t r p n m l k j h g f e d c b a 12 3 4 5 6 7 8 91011121314151617181920
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 42 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5.4 output buffer dc impedance the 750fx 60x drivers were characterized over various process, voltage, and temperature conditions. to measure z 0 , an external resistor is connected to the chip pad, either to ov dd or gnd. then the value of such resistor is varied until the pad voltage is ov dd /2 (see figure 5-6). the output impedance is actually the average of two resistances: the resistance of the pull-up and the resis- tance of pull-down devices. when data is held low, sw1 is closed (sw2 is open), and r n is trimmed until pad=ov dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw2 is closed (sw1 is open), and r p is trimmed until pad = ov dd /2. r p then becomes the resistance of the pull-up devices. with a properly designed driver r p and r n are close to each other in value, then z 0 = (r p + r n )/2. figure 5-6. driver impedance measurement data ov dd r p sw2 sw1 pad r n gnd
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 43 of 63 table 5-5 summarizes the driver impedance characteristics a designer uses to design a typical process. 5.4.1 input-output usage table 5-6 input-output usage provides details on the input-output usage of the powerpc 750fx risc micro- processor signals. the usage group column refers to the general functional category of the signal. in the powerpc 750fx risc microprocessor, certain input-output signals have pullups and pulldowns, which may or may not be enabled. in table 5-6, the input/output with internal resistors column defines which signals have these pullups or pulldowns and their active or inactive state. the level protect column defines which signals have the designated function added to their input/output cell. for more about level protection, see section 5.5 level protection on page 48. caution: this section is based on preliminary information and is subject to change. pull l2_tstclk and lssd_mode high for normal operation. pins shown as no connect (nc) must not be connected. connect all gnd pins to ground. connect all v dd and ov dd pins to the appropriate supply. table 5-5. driver impedance characteristics process 60x impedance ( ? ) ov dd (v) temperature ( c) worst 50 1.70 105 typical 44 1.80 65 best 36 1.90 0 worst 50 238 105 typical 44 2.50 65 best 36 2.63 0 worst 65 3.14 105 typical 50 3.30 65 best 35 3.46 0
datasheet dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 44 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 table 5-6. input-output usage 750fx signal name active level input/ output usage group input/output with internal pullup resistors level protect required external resistor comments notes a1v dd power supply a2v dd power supply a[0:31] high input/output address bus keeper 1, 3, 4 aack low input address termination keeper must be actively driven 3, 4, 5 abb low input/output keeper 5k ? pullup required to ov dd 3, 4, 5 agnd power supply ap[0:3] high input/output keeper 3, 4 artry low input/output address termination keeper 5k ? pullup required to ov dd 3, 4, 5 bg low input address arbitration keeper active driver or pulldown 3, 4, 5 br low output address arbitration keeper chip actively drives 3, 4, 5 bvsel n/a input input/output level 5k ? pullup/pulldown, as required 5 checkstop low output interrupt/resets keeper 5k ? pullup required to ov dd 3, 4, 5 ci low output transfer attributes keeper 1, 3, 4 ckstp_in low input interrupt/resets keeper must be actively driven 3, 4, 5 clk_out high output keeper 3, 4 dbb low input/output keeper 5k ? pullup required to ov dd 3, 4, 5 dbdis low input keeper 3, 4 dbg low input data arbitration keeper active driver or tie low 3, 4, 5 dbwo low input keeper 3, 4 notes: 1. depends on the system design. the electrical characteristics of the 750fx do not add additional constraints to the system design, so whatever is don e with the net will depend on the system require- ments. 2. hreset, sreset, and trst are signals used for esp and riscwatch to enable proper operation of the debuggers. logical and gates should be placed bet ween these signals and powerpc 750fx risc microprocessor. (refer to figure 5-7 on page 48.) 3. the 750fx provides protection from meta-stability on inputs through the use of a keeper circuit on specific inputs. refer t o level protection on page 48 for a more detailed description. 4. if a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be used (keepers assu re no meta-stability of inputs but do not guarantee a level). 5. the 750fx does not require external pullups on address and data lines. control lines must be treated individually.
datasheet dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 45 of 63 dh[0:31] high input/output data bus keeper 1, 3, 4 dl[0:31] high input/output data bus keeper 1, 3, 4 dp[0:7] high input/output drtry low input keeper 3, 4 gbl low input/output transfer attributes keeper 1, 3, 4 gnd power supply hreset low input interrupt/resets keeper active driver 2, 3, 4, 5 int low input interrupt/resets keeper active driver or pullup 3, 4, 5 l1_tstclk high input lssd not enabled 5k ? pullup/pulldown, as required 5 l2_tstclk high input lssd not enabled 5k ? pullup required to ov dd 5 lssd_mode low input lssd not enabled 5k ? pullup required to ov dd 5 mcp low input interrupt/resets keeper active driver or pullup 3, 4, 5 ov dd power supply pll_cfg[0:4] high input clock control keeper as required pullup/pulldown, as required 3, 4, 5 pll_rng[0:1] high input keeper as required pullup/pulldown, as required 3, 4, 5 qack low input control keeper must be actively driven 3, 4, 5 qreq low output status/control keeper chip actively drives 3, 4, 5 rsrv low output keeper no connect 3, 4, 5 smi low input keeper 3, 4 sreset low input interrupt/resets keeper active driver or pullup 2, 3, 4, 5 table 5-6. input-output usage (continued) 750fx signal name active level input/ output usage group input/output with internal pullup resistors level protect required external resistor comments notes notes: 1. depends on the system design. the electrical characteristics of the 750fx do not add additional constraints to the system design, so whatever is don e with the net will depend on the system require- ments. 2. hreset, sreset, and trst are signals used for esp and riscwatch to enable proper operation of the debuggers. logical and gates should be placed bet ween these signals and powerpc 750fx risc microprocessor. (refer to figure 5-7 on page 48.) 3. the 750fx provides protection from meta-stability on inputs through the use of a keeper circuit on specific inputs. refer t o level protection on page 48 for a more detailed description. 4. if a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be used (keepers assu re no meta-stability of inputs but do not guarantee a level). 5. the 750fx does not require external pullups on address and data lines. control lines must be treated individually.
datasheet dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 46 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 sysclk high input clock control keeper no resistor by design active driver 3, 4, 5 ta low input data termination keeper active driver 3, 4, 5 tben high input tbst low input/output transfer attributes keeper 1, 3, 4 tck high input jtag not enabled external pulldown 5k ? to gnd 5 tdi high input jtag enabled high internal enabled 50 a@2.5v 25 a@1.8v (the pullup current for the inter- nal resistor) 5 tdo high output jtag keeper 3, 4 tea low input data termination keeper active driver or pullup 3, 4, 5 tlbisync low input control keeper must be actively driven 3, 4 tms high input jtag enabled high internal enabled 50 a@2.5v 25 a@1.8v (the pullup current for the inter- nal resistor) 5 trst low input jtag enabled high internal enabled 50 a@2.5v 25 a@1.8v (the pullup current for the inter- nal resistor) 2, 5 ts low input/output address start keeper 5k ? pullup required to ov dd 3, 4, 5 tsiz[0:2] high output transfer attributes keeper 1, 3, 4 table 5-6. input-output usage (continued) 750fx signal name active level input/ output usage group input/output with internal pullup resistors level protect required external resistor comments notes notes: 1. depends on the system design. the electrical characteristics of the 750fx do not add additional constraints to the system design, so whatever is don e with the net will depend on the system require- ments. 2. hreset, sreset, and trst are signals used for esp and riscwatch to enable proper operation of the debuggers. logical and gates should be placed bet ween these signals and powerpc 750fx risc microprocessor. (refer to figure 5-7 on page 48.) 3. the 750fx provides protection from meta-stability on inputs through the use of a keeper circuit on specific inputs. refer t o level protection on page 48 for a more detailed description. 4. if a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be used (keepers assu re no meta-stability of inputs but do not guarantee a level). 5. the 750fx does not require external pullups on address and data lines. control lines must be treated individually.
datasheet dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 47 of 63 tt[0:4] high input/output transfer attributes keeper 1, 3, 4 v dd power supply wt low output transfer attributes keeper 1, 3, 4 table 5-6. input-output usage (continued) 750fx signal name active level input/ output usage group input/output with internal pullup resistors level protect required external resistor comments notes notes: 1. depends on the system design. the electrical characteristics of the 750fx do not add additional constraints to the system design, so whatever is don e with the net will depend on the system require- ments. 2. hreset, sreset, and trst are signals used for esp and riscwatch to enable proper operation of the debuggers. logical and gates should be placed bet ween these signals and powerpc 750fx risc microprocessor. (refer to figure 5-7 on page 48.) 3. the 750fx provides protection from meta-stability on inputs through the use of a keeper circuit on specific inputs. refer t o level protection on page 48 for a more detailed description. 4. if a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be used (keepers assu re no meta-stability of inputs but do not guarantee a level). 5. the 750fx does not require external pullups on address and data lines. control lines must be treated individually.
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 48 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5.5 level protection a level protection feature is included in the powerpc 750fx risc microprocessor. the level protection feature is available in the 1.8v, 2.5v, and 3.3v bus modes. this feature prevents ambiguous floating refer- ence voltages by pulling the respective signal line to the last valid or nearest valid state. for example, if the input/output voltage level is closer to ov dd , the circuit pulls the i/o level to ov dd. if the i/o level is closer to gnd, the i/o level is pulled low. this self-latching circuitry keeps the floating inputs defined and avoids meta-stability. in table 5-6 input-output usage on page 44, these signals are defined as keeper in the level protect column. keepers are not intended to force a net to a particular state. the keeper supplies a small (100 a max.) amount of current, which is intended to help keep a net at the current logic state. the level protect circuitry provides no additional leakage current to the signal i/o; however, some amount of current must be applied to the keeper node to overcome the level protection latch. this current is process dependent, but in no case is the current required over 100 a. this feature allows the system designer to limit the number of resistors in the design and optimize placement and reduce costs. note: having a level protection (keeper ) on the associated signal i/o does not replace a pull-up or pull-down resistor that is needed by the 750fx or a separate device located on the 60x bus. the designer must supply any such resisters. figure 5-7. ibm riscwatch tm jtag to hreset, trst, and sreset signal connector note: see notes for table 5-6 input-output usage on page 44. hreset from riscwatch system hreset hreset to powerpc 750fx trst to powerpc 750fx sreset to powerpc 750fx sreset from riscwatch system sreset trst from riscwatch
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 49 of 63 5.6 64 or 32-bit data bus mode this mode selection varies for different design revision (dd) levels. for the 750fx dd2.x, mode setting is determined by the state of the mode signal, tlbisync, at the transition of hreset from low to high. if tlbi- sync is high when hreset transitions from active to inactive, 64-bit mode is selected. if tlbisync is low when hreset transitions from active to inactive, 32-bit mode is selected. special note: (reduced pin out mode) to transition from a previous processor with reduced pin out mode, drive tlbisync appropriately, leave the dp(0..7) and ap(0..3) pins floating, and disable par- ity checking. the 750fx does not have ape and dpe pins. 5.7 i i o voltage mode selection selection between 1.8v, 2.5v, or 3.3v i/o modes is accomplished by using the bvsel and l1_tstclk pins: if bvsel = 1 and l1_tstclk = 0, then the 3.3v mode is enabled. if bvsel = 1 and l1_tstclk = 1, then the 2.5v mode is enabled. if bvsel = 0 and l1_tstclk = 1, then the 1.8v mode is enabled. note: do not set bvsel = 0 and l1_tstclk = 0 since it yields an invalid mode. 5.8 thermal management this section provides thermal management information for the cbga package for air cooled applications. proper thermal control design is primarily dependent upon the system-level design; that is, the heat sink, air flow, and the thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package, mounting clip, or a screw assembly, see figure 5-10 package exploded cross-sectional view with several heat sink options on page 54. in general, a heat sink is required for all 750fx applications. a design example is included in this section. 5.8.1 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: table 5-7. summary of mode select mode 750fx (dd2.x) 32-bit mode sample tlbisync to select high = 64-bit mode low = 32-bit mode i/o mode selection 3.3v +/- 165mv (bvsel = 1, l1_tstclk = 0) or 2.5v +/- 125mv (bvsel = 1, l1_tstclk = 1) or 1.8v +/- 100mv (bvsel = 0, l1_tstclk = 1)
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 50 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 t j = t a + t r + ( jc + int + sa ) p d where : t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the system cabinet jc is the junction-to-case thermal resistance int is the thermal resistance of the thermal interface material sa is the heat sink-to-ambient thermal resistance p d is the power dissipated by the device typical die-junction temperatures (t j ) should be maintained less than the value specified in table 3-3 package thermal characteristics1 on page 10. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the computer cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the interface material ( int ) is typically about 1 c/w. assuming a t a of 30 c,at r of 5 c, a cbga package jc = 0.03, and a power dissipation (p d )of 5.0 watts, the following expression for t j is obtained. die-junction temperature: t j = 30 c + 5 c + (0.03 c/w +1.0 c/w + sa ) 5w for a thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance ( sa ) versus air flow velocity is shown in figure 5-8 thermalloy #2328b pin-fin heat sink-to-ambient thermal resistance vs. airflow velocity on page 51.
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 51 of 63 assuming an air velocity of 0.5m/s, we have an effective sa of 7 c/w, thus t j = 30 c + 5 c + (2.2 c /w +1.0 c /w + 7 c /w) 4.5w, resulting in a junction temperature of approximately 81 c which is well within the maximum operating temperature of the component. other heat sinks offered by chip coolers, ierc, thermalloy, aavid, and wakefield engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. though the junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technolo- gies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. the final chip-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power dissipation, a number of factors affect the final operating die-junction temperature. these factors might include air flow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, next-level interconnect technology, system air temperature rise, and so forth. figure 5-8. thermalloy #2328b pin-fin heat sink-to-ambient thermal resistance vs. air?w velocity approach air velocity (m/s) heat sink thermal resistance ( c/w) 1 2 3 4 5 6 7 8 0 0.5 1 1.5 2 2.5 3 3.5 thermalloy #2328b pin-?n heat sink (25 x 28 x 15 mm)
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 52 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5.8.2 internal package conduction for the exposed-die packaging technology, shown in table 3-3 package thermal characteristics1 on page 10, the intrinsic conduction thermal resistance paths are as follows. die junction-to-case thermal resistance (primary thermal path) die junction-to-lead thermal resistance (not normally a signi?ant thermal path) die junction-to-ambient thermal resistance (largely dependent on customer-supplied heatsink) figure 5-9 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. heat generated on the active side (ball) of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink; where it is removed by forced- air convection. since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. thus, the heat sink attach material and the heat sink conduc- tion/convective thermal resistances are the dominant terms. the heat flow path from the die, through the chip-to-substrate balls, through the substrate, through the substrate-to-board balls, and through the board to ambient is usually too high of a resistance to offer much cooling. in addition, various factors make the heat flow through this path very difficult to accurately determine. designers must not depend on cooling the 750fx using this means unless thermal modeling has been confi- dently completed. figure 5-9. c4 package with heat sink mounted to a printed-circuit board external resistance external resistance internal (note the internal versus external package resistance.) radiation convection radiation convection heat sink die/package printed-circuit board thermal interface material package/leads chip junction resistance
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 53 of 63 5.8.3 minimum heat sink requirements the worst-case power dissipation (pd) for the 750fx is shown in table 3-5. a conservative thermal manage- ment design will provide sufficient cooling to maintain the junction temperature (t j ) of the 750fx below 105c at maximum pd and worst-case ambient temperature and airflow conditions. many factors affect the 750fx power dissipation, including v dd ,t j , core frequency, process factors, and the code that is running on the processor. in general, pd increases with increases in t j , v dd , fcore, process variables, and the number of instructions executed per second. for various reasons, a designer may determine that the power dissipation of the 750fx in their application will be less than the maximum value shown in the datasheet. assuming a lower pd will result in a thermal management system with less cooling capacity than would be required for the maximum datasheet pd. in this case, the designer may decide to determine the actual maximum 750fx pd in the particular application. contact your ibm powerpc fae for more information. in addition to the system factors that must be considered in a cooling system analysis, three things should be noted. first, 750fx pd rises as t j increases, so it is most useful to measure pd while the 750fx junction temperature is at maximum. while not specified or guaranteed, this rise in pd with t j is typically less than 1w per 10c. so regardless of other factors, the minimum cooling solution must have a maximum temperature rise of no more than 10c/w. this minimum cooling solution is not generally achievable without a heat sink. a heat sink or heat spreader of some sort must always be used in 750fx applications. second, due to process variations, there can be a significant variation in the pd of individual 750fx devices. in addition, ibm will occasionally supply "downbinned" parts. these are faster parts that are shipped in lieu of the speed that was ordered. for example, some parts that are marked as 600mhz may actually run as fast as 700mhz. these 700mhz parts will dissipate more power at 600mhz than the 600mhz parts. so power dissi- pation analysis should be conducted using the fastest parts available. finally, regardless of methodology, ibm only supports system designs that successfully maintain the maximum junction temperature within datasheet limits. ibm also supports designs that rely on the maximum pd values given in this datasheet, and supply a cooling solution sufficient to dissipate that amount of power while keeping the maximum junction temperature below the maximum t j .
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 54 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5.8.4 heat sink mounting 5.8.5 thermal assist unit the thermal sensor in the thermal assist unit (tau) has not been characterized to determine the basic uncalibrated accuracy. the relationship between the actual junction temperature and the temperature indi- cated by thrm1 and thrm2 is not well known. ibm recommends that the tau in these devices be calibrated before use. calibration methods are discussed in the ibm application note calibrating the thermal assist unit in the ibm25ppc750l processors . although this note was written for the 750l, the calibration methods discussed in this document also apply to the 750fx. in rare cases, the basic error of the tau may be so large that a useful calibration cannot be achieved. figure 5-10. package exploded cross-sectional view with several heat sink options table 5-8. maximum heatsink weight limit for the cbga force maximum maximum dynamic compressive force allowed on the bga balls 42.9 n maximum dynamic tensile force allowed on the bga balls 9.05 n maximum dynamic compressive force allowed on the chip 14.8 n maximum mass of module + heatsink when heatsink is not bolted to card 50g cbga package heat sink heat sink clip adhesive or thermal interface material printed option circuit board
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 55 of 63 5.8.6 adhesives and thermal interface materials a thermal interface material is recommended at the package die-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by a spring clip mecha- nism, figure 5-11 shows the thermal performance of three thin-sheet thermal-interface materials (silicon, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease, as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. in this example, the heat sink is attached to the package by means of a spring clip to holes in the printed- circuit board (see figure 5-10 package exploded cross-sectional view with several heat sink options on page 54). the synthetic grease offers the best thermal performance, considering the low interface pressure. the selection of any thermal interface material depends on many factors ?thermal performance require- ments, manufacturability, service temperature, dielectric properties, cost, and so forth. figure 5-11. thermal performance of select thermal interface material speci?c thermal resistance (kin 2 /w) 0 0.5 1 1.5 2 0 10 20 30 40 50 60 70 80 contact pressure (psi) + + + silicone sheet (0.006 inch) bare joint floroether oil sheet (0.007 inch) graphite/oil sheet (0.005 inch) synthetic grease +
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 56 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5.8.7 thermal interface and adhesive vendors the board designer can choose between several types of thermal interfaces. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. a partial list of vendors that advertise thermal interface materials for powerpc devices is shown in table 5-9 on page 56. table 5-9. 750fx thermal interface and adhesive materials vendors company names and addresses for thermal interfaces and adhesive materials vendors dow-corning corporation dow-corning electronic materials p.o. box 0997 midland, mi 48686-0997 (989) 496-4000 http://www.dowcorning.com/content/etronics chomerics, inc. 77 dragon court woburn, ma 01888-4850 (781) 935-4850 http://www.chomerics.com thermagon, inc. 4797 detroit avenue cleveland, oh 44102-2216 (216) 939-2300 / (888) 246-9050 http://www.thermagon.com loctite corporation 1001 trout brook crossing rocky hill, ct 06067 (860) 571-5100 / (800) 562-8483 http://www.loctite.com ai technology 70 washington road princeton, nj 08550-1097 (609) 799-9388 http://www.aitechnology.com
dd 2.x preliminary powerpc 750fx risc microprocessor body_750fx_ds_dd2.x.fm.2.0 june 9, 2003 5. system design information page 57 of 63 5.8.8 heat sink vendors the board designer can choose between several types of heat sinks to place on the 750fx. a partial list of vendors that advertise heat sinks for power pc devices is shown in table 5-10 a partial listing of 750fx heat sink vendors on page 57. table 5-10. a partial listing of 750fx heat sink vendors company names and addresses for heat sink vendors chip coolers, inc. 333 strawberry field rd. warwick, ri 02886 (800) 227-0254 http://www.chipcoolers.com international electronic research corporation (ierc) 413 north moss street burbank, ca 91502 (818) 842-7277 http://www.ctscorp.com/ierc aavid thermalloy 80 commercial street concord, nh 03301 (603) 224-9888 http://www.aavid.com http://www.aavidthermalloy.com wakefield thermal solutions inc. 33 bridge street pellham, nh 03076 (603) 635-2800 http://www.wakefield.com
dd 2.x powerpc 750fx risc microprocessor preliminary 5. system design information page 58 of 63 body_750fx_ds_dd2.x.fm.2.0 june 9, 2003
dd2.x preliminary powerpc 750fx risc microprocessor rev_log_750fx_ds_dd2.x.fm.2.0 june 9, 2003 revision log page 59 of 59 revision log date description feb 13, 2003 version 0.1 initial preliminary version for general release of 750fx dd2.3. may 16, 2003 version 1.0 second preliminary version which includes input/updates from designers. may 23, 2003 version 2.0 third preliminary version which includes input/updates from designers. june 3, 2003 version 2.0 fourth preliminary version which includes input/updates from designers. june 5, 2003 version 2.0 changed from dd2.3 to dd2.x. also included designer updates. june 6, 2003 version 2.0 changed table 3-5 power consumption. june 9, 2003 version 2.0 removed rev bars..

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